AArch64 instruction encoders (integer core). Mirrors dynasm-rs plugin/src/arch/aarch64/opmap.rs bases + compiler.rs command semantics, and runtime/src/aarch64.rs immediate helpers. Fixed 32-bit little-endian words; PC-relative relocations use the arch-specific codes in relocations.nim (B/BCOND/ADR/ADRP/TBZ).

Imports

types, relocations, registers

Procs

proc a64Adr(a: var auto; base: uint32; rd: Register; lr: LabelRef; isAdrp: bool)
proc a64BfmI(a: var auto; base: uint32; rd, rn: Register; amt: int64; is64: bool; op: int): op: 0=lsl (Usubmod+Usubzero), 1=lsr, 2=asr (Ubits, imms in base).
proc a64BrLbl(a: var auto; base: uint32; lr: LabelRef; rel: int): b/bl/b.cond/ldr-literal: Offset(B/BCOND) on a zero field.
proc a64BrReg(a: var auto; base: uint32; rn: Register): br/blr/ret reg: R(5).
proc a64Cbx(a: var auto; base: uint32; rt: Register; lr: LabelRef): cbz/cbnz: R(0) + Offset(BCOND).
proc a64DupG(a: var auto; base: uint32; rd, rn: Register; is128: bool): dup Vn.<arr>, Rn/Wn: R(0), R(5), Q bit.
proc a64Fcmp0(a: var auto; base: uint32; rn: Register): fcmp/fcmpe with #0.0: Rm field stays zero.
proc a64FmovI(a: var auto; base: uint32; rd: Register; bits: uint32): fmov S/D, #imm: Special FLOAT_IMMEDIATE at 13.
proc a64Hlt(a: var auto; base: uint32; imm: int64): hlt/svc: Ubits(5,16).
proc a64LogicI(a: var auto; base: uint32; rd, rn: Register; imm: uint64; is64: bool): AND/ORR/EOR (immediate): Special LOGICAL_IMMEDIATE.
proc a64Mem9(a: var auto; base: uint32; rt, rn: Register; off: int64): Pre/post-index ldr/str: Sbits(12,9), range -256..255.
proc a64MemU(a: var auto; base: uint32; rt, rn: Register; off: int64; scale: int): Unsigned-offset ldr/str: Uscaled(10,12,scale). Scale is 3 for 64-bit transfers, 2 for 32-bit (picked statically by the macro).
proc a64MemX(a: var auto; base: uint32; rt, rn, rm: Register; ext, amt: int64; scale: int): Register-offset ldr/str: ExtendsX(13) + S bit at 12. ext: 0=lsl, 1=sxtx (64-bit index); 2=sxtw, 4=uxtw (32-bit index).
proc a64Misc(a: var auto; base: uint32)
proc a64Movi(a: var auto; base: uint32; rd: Register; imm: uint64; shift: int64; isH: bool; is128: bool): movi Vn.4S/2S/H, #imm8 (, lsl): imm split over 9:5+18:16, shift/8 index at 14:13, Q bit at 30. H takes lsl #0/#8, S takes lsl #0/#8/#16/#24 (rs Ulist rows).
proc a64MovI(a: var auto; rd: Register; imm: uint64; is64: bool): Plain mov with immediate: MOVZ pattern only (rs WIDE_IMMEDIATE), i.e. a single 16-bit halfword slice. Anything else is an error (use mov.logical / explicit movz+movk for the rest).
proc a64MoviD(a: var auto; base: uint32; rd: Register; imm: uint64; is128: bool): movi Dn/2D, #stretched: STRETCHED_IMMEDIATE split over 9:5+18:16, Q bit at 30.
proc a64MovInv(a: var auto; rd: Register; imm: uint64; is64: bool): mov.inverted: MOVN pattern over the bitwise complement.
proc a64MovLogic(a: var auto; rd: Register; imm: uint64; is64: bool): mov.logical: ORR with a bitmask immediate (Rn=XZR baked in the base; the passed XZR ORs back to the same bits).
proc a64MovWide(a: var auto; base: uint32; rd: Register; imm16: uint64; shiftAmt: int64; is64: bool): movz/movn/movk: Ubits(5,16) + Ulist(21,0,16(,32,48)).
proc a64Pair(a: var auto; base: uint32; rt1, rt2, rn: Register; off: int64; scale: int): ldp/stp: Sscaled(15,7,scale), range +-64 scaled units (scale picked statically by the macro: 3 for X, 2 for W).
proc a64Reloc(a: var auto; lr: LabelRef; rel: int): Register a PC-relative fixup on the just-emitted word. fieldOffset=4, refOffset=4: value = target - instruction address.
proc a64RR(a: var auto; base: uint32; rd, rm: Register): R(0), R(16): mov (ORR), mvn.
proc a64RRI12(a: var auto; base: uint32; rd, rn: Register; imm: int64; shift: int64): ADD/SUB (immediate): Ubits(10,12) + Ulist(22,0,12).
proc a64RRn(a: var auto; base: uint32; rd, rn: Register): R(0), R(5): two-operand FP (fmov, fneg, scvtf, ...).
proc a64RRR(a: var auto; base: uint32; rd, rn, rm: Register)
proc a64RRRR(a: var auto; base: uint32; rd, rn, rm, ra: Register): +R(10): madd/msub.
proc a64RRSh(a: var auto; base: uint32; rd, rn, rm: Register; shift, amt: int64; is64: bool): Shifted/rotated register: Rotates(22) + Ubits(10,6/5). shift: 0=lsl, 1=lsr, 2=asr, 3=ror.
proc a64Tbx(a: var auto; base: uint32; rt: Register; bit: int64; lr: LabelRef; is64: bool): tbz/tbnz: bit split over 19-23 (+31 for 64-bit).
proc a64VecRR(a: var auto; base: uint32; rd, rn: Register; is128: bool): Vector 2-operand (fneg/fabs/fsqrt scalar uses fRR; vector forms go through here for the Q bit).
proc a64VecRRR(a: var auto; base: uint32; rd, rn, rm: Register; is128: bool): Vector ALU (add/sub/mul/and/orr/eor/bic, fadd/...): RRR + Q bit.
proc a64XRR(a: var auto; base: uint32; rn, rm: Register): R(5), R(16): cmp/tst (shifted register, XZR dest baked in base).
proc badImm(msg: string): ref DynasmError {....raises: [], tags: [], forbids: [].}
proc encodeFloatImm(bits: uint32): int {....raises: [], tags: [], forbids: [].}: Floating-point immediate (fmov), or -1. Port of dynasm-rs encode_floating_point_immediate: abcdefgh => aBbbbbbc defgh000 ... with B = !b.
proc encodeLogical32(value: uint32): int {....raises: [], tags: [], forbids: [].}: Logical (ORR/AND/EOR) 32-bit immediate N:immr:imms, or -1.
proc encodeLogical64(value: uint64): int {....raises: [], tags: [], forbids: [].}: 64-bit logical immediate N:immr:imms packed in 13 bits, or -1.
proc encodeStretchedImm(value: uint64): int {....raises: [], tags: [], forbids: [].}: 64-bit vector (movi d2) immediate, or -1. Port of dynasm-rs encode_stretched_immediate.
proc encodeWide32(value: uint32): int {....raises: [], tags: [], forbids: [].}
proc encodeWide64(value: uint64): int {....raises: [], tags: [], forbids: [].}: MOVZ/MOVK-style 64-bit immediate, or -1. Encoded as imm16 | hw-shift (rs encode_wide_immediate_64bit).

dynasm/aarch64

Imports

Procs