dynasm/registers

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Register definitions for x64/x86 (+ AArch64 Xn/Wn/SP/XZR). Runtime codes match references/dynasm-rs/runtime/src/x64.rs, x86.rs and aarch64.rs.

Types

LabelRef = object
  case isLabel*: bool
  of true:
    lkind*: LabelRefKind
    lname*: string
    dynExpr*: string         ## placeholder, real expr handled in macro via id
    dynId*: int              ## resolved at macro expansion when possible
    loff*: int
  of false:
    nil
LabelRefKind = enum
  lrForward, lrBackward, lrGlobal, lrDynamic, lrAbsolute
MemOp = object
  hasBase*: bool
  base*: Register
  hasIndex*: bool
  index*: Register
  scale*: int
  disp*: int64
  hasDisp*: bool
  ripLabel*: LabelRef        ## for [glob(..)] / [fwd(..)] RIP-relative
  hasRip*: bool
  addrSizeOverride*: bool
Operand = object
  case kind*: OperandKind
  of okReg:
    reg*: Register
    regSize*: OpSize
  of okImm:
    imm*: int64
    immSize*: OpSize
  of okMem:
    mem*: MemOp
    memSize*: OpSize
  of okLabelRef:
    lbl*: LabelRef
OperandKind = enum
  okReg, okImm, okMem, okLabelRef
OpSize = enum
  szNone, sz8, sz16, sz32, sz64
RegClass = enum
  rcGpr,                    ## general purpose (size encoded separately)
  rcHigh8,                  ## AH/CH/DH/BH
  rcFpu,                    ## ST0..7
  rcMmx, rcXmm, rcSeg, rcControl, rcDebug, rcBound
Register = object
  code*: uint8
  cls*: RegClass

Consts

A64ExtLsl = 0
ah = (code: 4'u, cls: rcHigh8)
al = (code: 0'u, cls: rcGpr)
ax = (code: 0'u, cls: rcGpr)
bh = (code: 7'u, cls: rcHigh8)
bl = (code: 3'u, cls: rcGpr)
bp = (code: 5'u, cls: rcGpr)
bpl = (code: 5'u, cls: rcGpr)
bx = (code: 3'u, cls: rcGpr)
ch = (code: 5'u, cls: rcHigh8)
cl = (code: 1'u, cls: rcGpr)
cx = (code: 1'u, cls: rcGpr)
dh = (code: 6'u, cls: rcHigh8)
di = (code: 7'u, cls: rcGpr)
dil = (code: 7'u, cls: rcGpr)
dl = (code: 2'u, cls: rcGpr)
dx = (code: 2'u, cls: rcGpr)
eax = (code: 0'u, cls: rcGpr)
ebp = (code: 5'u, cls: rcGpr)
ebx = (code: 3'u, cls: rcGpr)
ecx = (code: 1'u, cls: rcGpr)
edi = (code: 7'u, cls: rcGpr)
edx = (code: 2'u, cls: rcGpr)
esi = (code: 6'u, cls: rcGpr)
esp = (code: 4'u, cls: rcGpr)
r8 = (code: 8'u, cls: rcGpr)
r8b = (code: 8'u, cls: rcGpr)
r8d = (code: 8'u, cls: rcGpr)
r9 = (code: 9'u, cls: rcGpr)
r9b = (code: 9'u, cls: rcGpr)
r9d = (code: 9'u, cls: rcGpr)
r10 = (code: 10'u, cls: rcGpr)
r10b = (code: 10'u, cls: rcGpr)
r10d = (code: 10'u, cls: rcGpr)
r11 = (code: 11'u, cls: rcGpr)
r11b = (code: 11'u, cls: rcGpr)
r11d = (code: 11'u, cls: rcGpr)
r12 = (code: 12'u, cls: rcGpr)
r12b = (code: 12'u, cls: rcGpr)
r12d = (code: 12'u, cls: rcGpr)
r13 = (code: 13'u, cls: rcGpr)
r13b = (code: 13'u, cls: rcGpr)
r13d = (code: 13'u, cls: rcGpr)
r14 = (code: 14'u, cls: rcGpr)
r14b = (code: 14'u, cls: rcGpr)
r14d = (code: 14'u, cls: rcGpr)
r15 = (code: 15'u, cls: rcGpr)
r15b = (code: 15'u, cls: rcGpr)
r15d = (code: 15'u, cls: rcGpr)
rax = (code: 0'u, cls: rcGpr)
rbp = (code: 5'u, cls: rcGpr)
rbx = (code: 3'u, cls: rcGpr)
rcx = (code: 1'u, cls: rcGpr)
rdi = (code: 7'u, cls: rcGpr)
rdx = (code: 2'u, cls: rcGpr)
rsi = (code: 6'u, cls: rcGpr)
rsp = (code: 4'u, cls: rcGpr)
si = (code: 6'u, cls: rcGpr)
sil = (code: 6'u, cls: rcGpr)
sp = (code: 4'u, cls: rcGpr)
spl = (code: 4'u, cls: rcGpr)
w0 = (code: 0'u, cls: rcGpr)
w1 = (code: 1'u, cls: rcGpr)
w2 = (code: 2'u, cls: rcGpr)
w3 = (code: 3'u, cls: rcGpr)
w4 = (code: 4'u, cls: rcGpr)
w5 = (code: 5'u, cls: rcGpr)
w6 = (code: 6'u, cls: rcGpr)
w7 = (code: 7'u, cls: rcGpr)
w8 = (code: 8'u, cls: rcGpr)
w9 = (code: 9'u, cls: rcGpr)
w10 = (code: 10'u, cls: rcGpr)
w11 = (code: 11'u, cls: rcGpr)
w12 = (code: 12'u, cls: rcGpr)
w13 = (code: 13'u, cls: rcGpr)
w14 = (code: 14'u, cls: rcGpr)
w15 = (code: 15'u, cls: rcGpr)
w16 = (code: 16'u, cls: rcGpr)
w17 = (code: 17'u, cls: rcGpr)
w18 = (code: 18'u, cls: rcGpr)
w19 = (code: 19'u, cls: rcGpr)
w20 = (code: 20'u, cls: rcGpr)
w21 = (code: 21'u, cls: rcGpr)
w22 = (code: 22'u, cls: rcGpr)
w23 = (code: 23'u, cls: rcGpr)
w24 = (code: 24'u, cls: rcGpr)
w25 = (code: 25'u, cls: rcGpr)
w26 = (code: 26'u, cls: rcGpr)
w27 = (code: 27'u, cls: rcGpr)
w28 = (code: 28'u, cls: rcGpr)
w29 = (code: 29'u, cls: rcGpr)
w30 = (code: 30'u, cls: rcGpr)
wsp = (code: 31'u, cls: rcGpr)
wzr = (code: 31'u, cls: rcGpr)
x0 = (code: 0'u, cls: rcGpr)
x1 = (code: 1'u, cls: rcGpr)
x2 = (code: 2'u, cls: rcGpr)
x3 = (code: 3'u, cls: rcGpr)
x4 = (code: 4'u, cls: rcGpr)
x5 = (code: 5'u, cls: rcGpr)
x6 = (code: 6'u, cls: rcGpr)
x7 = (code: 7'u, cls: rcGpr)
x8 = (code: 8'u, cls: rcGpr)
x9 = (code: 9'u, cls: rcGpr)
x10 = (code: 10'u, cls: rcGpr)
x11 = (code: 11'u, cls: rcGpr)
x12 = (code: 12'u, cls: rcGpr)
x13 = (code: 13'u, cls: rcGpr)
x14 = (code: 14'u, cls: rcGpr)
x15 = (code: 15'u, cls: rcGpr)
x16 = (code: 16'u, cls: rcGpr)
x17 = (code: 17'u, cls: rcGpr)
x18 = (code: 18'u, cls: rcGpr)
x19 = (code: 19'u, cls: rcGpr)
x20 = (code: 20'u, cls: rcGpr)
x21 = (code: 21'u, cls: rcGpr)
x22 = (code: 22'u, cls: rcGpr)
x23 = (code: 23'u, cls: rcGpr)
x24 = (code: 24'u, cls: rcGpr)
x25 = (code: 25'u, cls: rcGpr)
x26 = (code: 26'u, cls: rcGpr)
x27 = (code: 27'u, cls: rcGpr)
x28 = (code: 28'u, cls: rcGpr)
x29 = (code: 29'u, cls: rcGpr)
x30 = (code: 30'u, cls: rcGpr)
xmm0 = (code: 0'u, cls: rcXmm)
xmm1 = (code: 1'u, cls: rcXmm)
xmm2 = (code: 2'u, cls: rcXmm)
xmm3 = (code: 3'u, cls: rcXmm)
xmm4 = (code: 4'u, cls: rcXmm)
xmm5 = (code: 5'u, cls: rcXmm)
xmm6 = (code: 6'u, cls: rcXmm)
xmm7 = (code: 7'u, cls: rcXmm)
xmm8 = (code: 8'u, cls: rcXmm)
xmm9 = (code: 9'u, cls: rcXmm)
xmm10 = (code: 10'u, cls: rcXmm)
xmm11 = (code: 11'u, cls: rcXmm)
xmm12 = (code: 12'u, cls: rcXmm)
xmm13 = (code: 13'u, cls: rcXmm)
xmm14 = (code: 14'u, cls: rcXmm)
xmm15 = (code: 15'u, cls: rcXmm)
xsp = (code: 31'u, cls: rcGpr)
xzr = (code: 31'u, cls: rcGpr)

Procs

proc bwd(name: string; off: int = 0): LabelRef {....raises: [], tags: [],
    forbids: [].}
proc byte(m: MemOp): Operand {....raises: [], tags: [], forbids: [].}
proc byte(r: Register): Operand {....raises: [], tags: [], forbids: [].}
proc byte(v: int64): Operand {....raises: [], tags: [], forbids: [].}
proc dword(m: MemOp): Operand {....raises: [], tags: [], forbids: [].}
proc dword(r: Register): Operand {....raises: [], tags: [], forbids: [].}
proc dword(v: int64): Operand {....raises: [], tags: [], forbids: [].}
proc dyn(id: DynamicLabel; off: int = 0): LabelRef {.inline, ...raises: [],
    tags: [], forbids: [].}
proc dyn(id: int; off: int = 0): LabelRef {.inline, ...raises: [], tags: [],
    forbids: [].}
proc dynLbl(id: DynamicLabel; off: int = 0): LabelRef {....raises: [], tags: [],
    forbids: [].}
proc dynLbl(id: int; off: int = 0): LabelRef {....raises: [], tags: [], forbids: [].}
proc extAddr(a: int; off: int = 0): LabelRef {....raises: [], tags: [], forbids: [].}
proc extAddrPtr(a: pointer; off: int = 0): LabelRef {....raises: [], tags: [],
    forbids: [].}
proc fwd(name: string; off: int = 0): LabelRef {....raises: [], tags: [],
    forbids: [].}
proc glob(name: string; off: int = 0): LabelRef {....raises: [], tags: [],
    forbids: [].}
proc immOp(v: int64; s: OpSize = szNone): Operand {....raises: [], tags: [],
    forbids: [].}
proc labelOp(l: LabelRef): Operand {....raises: [], tags: [], forbids: [].}
proc memOp(m: MemOp; s: OpSize = szNone): Operand {....raises: [], tags: [],
    forbids: [].}
proc qword(m: MemOp): Operand {....raises: [], tags: [], forbids: [].}
proc qword(r: Register): Operand {....raises: [], tags: [], forbids: [].}
proc qword(v: int64): Operand {....raises: [], tags: [], forbids: [].}
proc Rd(idx: int): Register {....raises: [], tags: [], forbids: [].}
proc regCode(r: Register): uint8 {....raises: [], tags: [], forbids: [].}
proc regOp(r: Register; s: OpSize = szNone): Operand {....raises: [], tags: [],
    forbids: [].}
proc Rq(idx: int): Register {....raises: [], tags: [], forbids: [].}
proc Rx(idx: int): Register {....raises: [], tags: [], forbids: [].}
proc word(m: MemOp): Operand {....raises: [], tags: [], forbids: [].}
proc word(r: Register): Operand {....raises: [], tags: [], forbids: [].}
proc word(v: int64): Operand {....raises: [], tags: [], forbids: [].}
proc Wreg(idx: int): Register {....raises: [], tags: [], forbids: [].}
proc Xreg(idx: int): Register {....raises: [], tags: [], forbids: [].}