AArch64 op tables: the Nim counterpart of dynasm-rs opmap.rs. Each entry is (base template bits, operand shapes, encoder form, relocation id). The macro matches operand shapes statically (like rs matching.rs) and emits a call to one runtime form in aarch64.nim (like rs compiler.rs commands). Bases below are transcribed from plugin/src/arch/aarch64/opmap.rs.
Types
A64Form = enum fRRR, ## R(0), R(5), R(16) fRR, ## R(0), R(16): mov reg, mvn fRRn, ## R(0), R(5): two-operand FP forms fXRR, ## R(5), R(16): cmp/tst reg (XZR dest in base) fRRRR, ## +R(10): madd/msub fRRI12, ## add/sub imm: Ubits(10,12) + lsl12 flag fLogicI, ## logical imm: Special LOGICAL_IMMEDIATE fMovI, ## plain mov imm: MOVZ pattern (WIDE_IMMEDIATE) fMovInv, ## mov.inverted: MOVN pattern over complement fMovLogic, ## mov.logical: ORR bitmask pattern fMovWide, ## movz/movn/movk: Ubits(5,16) + hw fBfmI, ## lsl/lsr/asr imm aliases fMemU, ## unsigned-offset ldr/str: Uscaled(10,12,s) fMem9, ## pre/post-index ldr/str: Sbits(12,9) fPair, ## ldp/stp: Sscaled(15,7,s) fMemX, ## register-offset ldr/str: ExtendsX + S bit fBr, ## b/bl/b.cond/ldr-literal + relocation fCbx, ## cbz/cbnz: R(0) + BCOND relocation fTbx, ## tbz/tbnz: split bit + TBZ relocation fAdr, ## adr/adrp: R(0) + ADR/ADRP relocation fBrReg, ## br/blr/ret reg: R(5) fMisc, ## fixed word: nop, ret fHlt, ## hlt/svc: Ubits(5,16) fFmovI, ## fmov S/D, #imm: Special FLOAT_IMMEDIATE at 13 fFcmp0, ## fcmp/fcmpe with #0.0: Rn only fVecRRR, ## vector ALU: RRR + Q bit fVecMovi, ## movi Vn.4S/2S/H/B, #imm8 (, lsl) fVecMoviD, ## movi Dn/2D, #stretched fDupG ## dup Vn.<arr>, Rn/Wn: R(0), R(5), Q bit
A64Shape = enum asX, ## 64-bit integer reg (incl. xzr, dynamic Xreg) asW, ## 32-bit integer reg (incl. wzr, dynamic Wreg) asXSP, ## asX plus sp asWSP, ## asW plus wsp asB, ## scalar SIMD byte reg b0-b31 asH, ## scalar SIMD halfword reg h0-h31 asS, ## scalar SIMD single reg s0-s31 asD, ## scalar SIMD double reg d0-d31 asQ, ## scalar SIMD quad reg q0-q31 asVeB, ## vector reg with byte elements: vN.b8/b16 asVeH, ## vector reg with halfword elements: vN.h4/h8 asVeS, ## vector reg with single elements: vN.s2/s4 asVeD, ## vector reg with double elements: vN.d1/d2 asImm, ## immediate: int literal or Nim expression asFImm, ## float immediate: float literal (fmov) asFZero, ## fcmp #0.0 marker (float literal 0.0) asMemBase, ## [base] asMemOff, ## [base, imm] asMemPre, ## [base, imm], pre-indexed (trailing `pre`) asMemPost, ## [base], imm (post-indexed) asMemIdx, ## [base, index (, extend (, amount))] asLbl, ## label reference (fwd/bwd/glob/dyn/extaddr-free) asMod, ## shift/extend modifier ident (lsl/lsr/asr/ror/...) asPre ## trailing `pre` marker
Consts
a64CondBits = [0, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
a64CondNames = ["eq", "ne", "cs", "hs", "cc", "lo", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"]
a64ExtendMods = ["uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx", "lsl"]
a64ShiftMods = ["lsl", "lsr", "asr", "ror"]
Procs
proc a64Entries(mn: string): seq[A64Entry] {....raises: [], tags: [], forbids: [].}
- All forms for a mnemonic, most specific first.
proc a64Mnemonics(): seq[string] {....raises: [], tags: [], forbids: [].}